\doxysection{Topics}
Here is a list of all topics with brief descriptions\+:\begin{DoxyCompactList}
\item \contentsline{section}{CMSIS Global Defines}{\pageref{group___c_m_s_i_s__glob__defs}}{}
\item \contentsline{section}{Defines and Type Definitions}{\pageref{group___c_m_s_i_s__core__register}}{}
\begin{DoxyCompactList}
\item \contentsline{section}{Status and Control Registers}{\pageref{group___c_m_s_i_s___c_o_r_e}}{}
\begin{DoxyCompactList}
\item \contentsline{section}{Nested Vectored Interrupt Controller (NVIC)}{\pageref{group___c_m_s_i_s___n_v_i_c}}{}
\begin{DoxyCompactList}
\item \contentsline{section}{System Control Block (SCB)}{\pageref{group___c_m_s_i_s___s_c_b}}{}
\begin{DoxyCompactList}
\item \contentsline{section}{System Controls not in SCB (SCn\+SCB)}{\pageref{group___c_m_s_i_s___s_cn_s_c_b}}{}
\begin{DoxyCompactList}
\item \contentsline{section}{System Tick Timer (Sys\+Tick)}{\pageref{group___c_m_s_i_s___sys_tick}}{}
\item \contentsline{section}{Instrumentation Trace Macrocell (ITM)}{\pageref{group___c_m_s_i_s___i_t_m}}{}
\item \contentsline{section}{Data Watchpoint and Trace (DWT)}{\pageref{group___c_m_s_i_s___d_w_t}}{}
\item \contentsline{section}{Trace Port Interface (TPI)}{\pageref{group___c_m_s_i_s___t_p_i}}{}
\item \contentsline{section}{Memory Protection Unit (MPU)}{\pageref{group___c_m_s_i_s___m_p_u}}{}
\item \contentsline{section}{Floating Point Unit (FPU)}{\pageref{group___c_m_s_i_s___f_p_u}}{}
\item \contentsline{section}{Core Debug Registers (Core\+Debug)}{\pageref{group___c_m_s_i_s___core_debug}}{}
\item \contentsline{section}{Core register bit field macros}{\pageref{group___c_m_s_i_s__core__bitfield}}{}
\item \contentsline{section}{Core Definitions}{\pageref{group___c_m_s_i_s__core__base}}{}
\item \contentsline{section}{Functions and Instructions Reference}{\pageref{group___c_m_s_i_s___core___function_interface}}{}
\item \contentsline{section}{CMSIS Core Register Access Functions}{\pageref{group___c_m_s_i_s___core___reg_acc_functions}}{}
\item \contentsline{section}{CMSIS Core Instruction Interface}{\pageref{group___c_m_s_i_s___core___instruction_interface}}{}
\item \contentsline{section}{CMSIS SIMD Intrinsics}{\pageref{group___c_m_s_i_s___s_i_m_d__intrinsics}}{}
\item \contentsline{section}{NVIC Functions}{\pageref{group___c_m_s_i_s___core___n_v_i_c_functions}}{}
\item \contentsline{section}{FPU Functions}{\pageref{group___c_m_s_i_s___core___fpu_functions}}{}
\item \contentsline{section}{SAU Functions}{\pageref{group___c_m_s_i_s___core___s_a_u_functions}}{}
\item \contentsline{section}{Sys\+Tick Functions}{\pageref{group___c_m_s_i_s___core___sys_tick_functions}}{}
\item \contentsline{section}{ITM Functions}{\pageref{group___c_m_s_i_s__core___debug_functions}}{}
\item \contentsline{section}{Cache Functions}{\pageref{group___c_m_s_i_s___core___cache_functions}}{}
\item \contentsline{section}{Sys\+Tick Functions}{\pageref{group___c_m_s_i_s___core___sys_tick_functions}}{}
\item \contentsline{section}{ITM Functions}{\pageref{group___c_m_s_i_s__core___debug_functions}}{}
\item \contentsline{section}{NVIC Functions}{\pageref{group___c_m_s_i_s___core___n_v_i_c_functions}}{}
\item \contentsline{section}{FPU Functions}{\pageref{group___c_m_s_i_s___core___fpu_functions}}{}
\item \contentsline{section}{SAU Functions}{\pageref{group___c_m_s_i_s___core___s_a_u_functions}}{}
\item \contentsline{section}{Sys\+Tick Functions}{\pageref{group___c_m_s_i_s___core___sys_tick_functions}}{}
\item \contentsline{section}{ITM Functions}{\pageref{group___c_m_s_i_s__core___debug_functions}}{}
\item \contentsline{section}{Cache Functions}{\pageref{group___c_m_s_i_s___core___cache_functions}}{}
\item \contentsline{section}{Sys\+Tick Functions}{\pageref{group___c_m_s_i_s___core___sys_tick_functions}}{}
\item \contentsline{section}{ITM Functions}{\pageref{group___c_m_s_i_s__core___debug_functions}}{}
\end{DoxyCompactList}
\end{DoxyCompactList}
\end{DoxyCompactList}
\end{DoxyCompactList}
\end{DoxyCompactList}
\item \contentsline{section}{HAL CRYP Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___a_e_s___aliased___defines}}{}
\item \contentsline{section}{HAL ADC Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___a_d_c___aliased___defines}}{}
\item \contentsline{section}{HAL CEC Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___c_e_c___aliased___defines}}{}
\item \contentsline{section}{HAL COMP Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___c_o_m_p___aliased___defines}}{}
\item \contentsline{section}{HAL CORTEX Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___c_o_r_t_e_x___aliased___defines}}{}
\item \contentsline{section}{CRC API aliases}{\pageref{group___c_r_c___aliases}}{}
\item \contentsline{section}{HAL CRC Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___c_r_c___aliased___defines}}{}
\item \contentsline{section}{HAL DAC Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___d_a_c___aliased___defines}}{}
\item \contentsline{section}{HAL DMA Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___d_m_a___aliased___defines}}{}
\item \contentsline{section}{HAL FLASH Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___f_l_a_s_h___aliased___defines}}{}
\item \contentsline{section}{HAL JPEG Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___j_p_e_g___aliased___macros}}{}
\item \contentsline{section}{HAL SYSCFG Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___s_y_s_c_f_g___aliased___defines}}{}
\item \contentsline{section}{LL FMC Aliased Defines maintained for compatibility purpose}{\pageref{group___l_l___f_m_c___aliased___defines}}{}
\item \contentsline{section}{LL FSMC Aliased Defines maintained for legacy purpose}{\pageref{group___l_l___f_s_m_c___aliased___defines}}{}
\item \contentsline{section}{HAL GPIO Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___g_p_i_o___aliased___macros}}{}
\item \contentsline{section}{HAL GTZC Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___g_t_z_c___aliased___defines}}{}
\item \contentsline{section}{HAL HRTIM Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___h_r_t_i_m___aliased___macros}}{}
\item \contentsline{section}{HAL I2C Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___i2_c___aliased___defines}}{}
\item \contentsline{section}{HAL IRDA Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___i_r_d_a___aliased___defines}}{}
\item \contentsline{section}{HAL IWDG Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___i_w_d_g___aliased___defines}}{}
\item \contentsline{section}{HAL LPTIM Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___l_p_t_i_m___aliased___defines}}{}
\item \contentsline{section}{HAL NAND Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___n_a_n_d___aliased___defines}}{}
\item \contentsline{section}{HAL NOR Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___n_o_r___aliased___defines}}{}
\item \contentsline{section}{HAL OPAMP Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___o_p_a_m_p___aliased___defines}}{}
\item \contentsline{section}{HAL I2S Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___i2_s___aliased___defines}}{}
\item \contentsline{section}{HAL PCCARD Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___p_c_c_a_r_d___aliased___defines}}{}
\item \contentsline{section}{HAL RTC Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___r_t_c___aliased___defines}}{}
\item \contentsline{section}{HAL SMARTCARD Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___s_m_a_r_t_c_a_r_d___aliased___defines}}{}
\item \contentsline{section}{HAL SMBUS Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___s_m_b_u_s___aliased___defines}}{}
\item \contentsline{section}{HAL SPI Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___s_p_i___aliased___defines}}{}
\item \contentsline{section}{HAL TIM Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___t_i_m___aliased___defines}}{}
\item \contentsline{section}{HAL TSC Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___t_s_c___aliased___defines}}{}
\item \contentsline{section}{HAL UART Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___u_a_r_t___aliased___defines}}{}
\item \contentsline{section}{HAL USART Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___u_s_a_r_t___aliased___defines}}{}
\item \contentsline{section}{HAL WWDG Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___w_w_d_g___aliased___defines}}{}
\item \contentsline{section}{HAL CAN Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___c_a_n___aliased___defines}}{}
\item \contentsline{section}{HAL ETH Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___e_t_h___aliased___defines}}{}
\item \contentsline{section}{HAL DCMI Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___d_c_m_i___aliased___defines}}{}
\item \contentsline{section}{HAL PPP Aliased Defines maintained for legacy purpose}{\pageref{group___h_a_l___p_p_p___aliased___defines}}{}
\item \contentsline{section}{HAL CRYP Aliased Functions maintained for legacy purpose}{\pageref{group___h_a_l___c_r_y_p___aliased___functions}}{}
\item \contentsline{section}{HAL DCACHE Aliased Functions maintained for legacy purpose}{\pageref{group___h_a_l___d_c_a_c_h_e___aliased___functions}}{}
\item \contentsline{section}{HASH API alias}{\pageref{group___h_a_s_h__alias}}{}
\item \contentsline{section}{HAL HASH Aliased Functions maintained for legacy purpose}{\pageref{group___h_a_l___h_a_s_h___aliased___functions}}{}
\item \contentsline{section}{HAL Generic Aliased Functions maintained for legacy purpose}{\pageref{group___h_a_l___aliased___functions}}{}
\item \contentsline{section}{HAL FLASH Aliased Functions maintained for legacy purpose}{\pageref{group___h_a_l___f_l_a_s_h___aliased___functions}}{}
\item \contentsline{section}{HAL I2C Aliased Functions maintained for legacy purpose}{\pageref{group___h_a_l___i2_c___aliased___functions}}{}
\item \contentsline{section}{HAL PWR Aliased maintained for legacy purpose}{\pageref{group___h_a_l___p_w_r___aliased}}{}
\item \contentsline{section}{HAL RTC Aliased Functions maintained for legacy purpose}{\pageref{group___h_a_l___r_t_c___aliased___functions}}{}
\item \contentsline{section}{HAL SMBUS Aliased Functions maintained for legacy purpose}{\pageref{group___h_a_l___s_m_b_u_s___aliased___functions}}{}
\item \contentsline{section}{HAL SPI Aliased Functions maintained for legacy purpose}{\pageref{group___h_a_l___s_p_i___aliased___functions}}{}
\item \contentsline{section}{HAL TIM Aliased Functions maintained for legacy purpose}{\pageref{group___h_a_l___t_i_m___aliased___functions}}{}
\item \contentsline{section}{HAL UART Aliased Functions maintained for legacy purpose}{\pageref{group___h_a_l___u_a_r_t___aliased___functions}}{}
\item \contentsline{section}{HAL LTDC Aliased Functions maintained for legacy purpose}{\pageref{group___h_a_l___l_t_d_c___aliased___functions}}{}
\item \contentsline{section}{HAL PPP Aliased Functions maintained for legacy purpose}{\pageref{group___h_a_l___p_p_p___aliased___functions}}{}
\item \contentsline{section}{HAL CRYP Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___a_e_s___aliased___macros}}{}
\item \contentsline{section}{HAL Generic Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___aliased___macros}}{}
\item \contentsline{section}{HAL ADC Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___a_d_c___aliased___macros}}{}
\item \contentsline{section}{HAL DAC Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___d_a_c___aliased___macros}}{}
\item \contentsline{section}{HAL DBGMCU Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___d_b_g_m_c_u___aliased___macros}}{}
\item \contentsline{section}{HAL COMP Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___c_o_m_p___aliased___macros}}{}
\item \contentsline{section}{HAL FLASH Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___f_l_a_s_h___aliased___macros}}{}
\item \contentsline{section}{HAL I2C Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___i2_c___aliased___macros}}{}
\item \contentsline{section}{HAL I2S Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___i2_s___aliased___macros}}{}
\item \contentsline{section}{HAL IRDA Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___i_r_d_a___aliased___macros}}{}
\item \contentsline{section}{HAL IWDG Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___i_w_d_g___aliased___macros}}{}
\item \contentsline{section}{HAL LPTIM Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___l_p_t_i_m___aliased___macros}}{}
\item \contentsline{section}{HAL OPAMP Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___o_p_a_m_p___aliased___macros}}{}
\item \contentsline{section}{HAL PWR Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___p_w_r___aliased___macros}}{}
\item \contentsline{section}{HAL RCC Aliased maintained for legacy purpose}{\pageref{group___h_a_l___r_c_c___aliased}}{}
\item \contentsline{section}{HAL RNG Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___r_n_g___aliased___macros}}{}
\item \contentsline{section}{HAL RTC Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___r_t_c___aliased___macros}}{}
\item \contentsline{section}{HAL SD/\+MMC Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___s_d___aliased___macros}}{}
\item \contentsline{section}{HAL SMARTCARD Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___s_m_a_r_t_c_a_r_d___aliased___macros}}{}
\item \contentsline{section}{HAL SMBUS Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___s_m_b_u_s___aliased___macros}}{}
\item \contentsline{section}{HAL SPI Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___s_p_i___aliased___macros}}{}
\item \contentsline{section}{HAL UART Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___u_a_r_t___aliased___macros}}{}
\item \contentsline{section}{HAL USART Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___u_s_a_r_t___aliased___macros}}{}
\item \contentsline{section}{HAL USB Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___u_s_b___aliased___macros}}{}
\item \contentsline{section}{HAL TIM Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___t_i_m___aliased___macros}}{}
\item \contentsline{section}{HAL ETH Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___e_t_h___aliased___macros}}{}
\item \contentsline{section}{HAL LTDC Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___l_t_d_c___aliased___macros}}{}
\item \contentsline{section}{HAL SAI Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___s_a_i___aliased___macros}}{}
\item \contentsline{section}{HAL SPDIFRX Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___s_p_d_i_f_r_x___aliased___macros}}{}
\item \contentsline{section}{HAL HRTIM Aliased Functions maintained for legacy purpose}{\pageref{group___h_a_l___h_r_t_i_m___aliased___functions}}{}
\item \contentsline{section}{HAL QSPI Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___q_s_p_i___aliased___macros}}{}
\item \contentsline{section}{HAL Generic Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___generic___aliased___macros}}{}
\item \contentsline{section}{HAL PPP Aliased Macros maintained for legacy purpose}{\pageref{group___h_a_l___p_p_p___aliased___macros}}{}
\item \contentsline{section}{Basic Math Functions}{\pageref{group__group_math}}{}
\item \contentsline{section}{Fast Math Functions}{\pageref{group__group_fast_math}}{}
\begin{DoxyCompactList}
\item \contentsline{section}{Square Root}{\pageref{group___s_q_r_t}}{}
\end{DoxyCompactList}
\item \contentsline{section}{Complex Math Functions}{\pageref{group__group_cmplx_math}}{}
\item \contentsline{section}{Filtering Functions}{\pageref{group__group_filters}}{}
\item \contentsline{section}{Matrix Functions}{\pageref{group__group_matrix}}{}
\item \contentsline{section}{Transform Functions}{\pageref{group__group_transforms}}{}
\item \contentsline{section}{Controller Functions}{\pageref{group__group_controller}}{}
\begin{DoxyCompactList}
\item \contentsline{section}{PID Motor Control}{\pageref{group___p_i_d}}{}
\item \contentsline{section}{Vector Clarke Transform}{\pageref{group__clarke}}{}
\item \contentsline{section}{Vector Inverse Clarke Transform}{\pageref{group__inv__clarke}}{}
\item \contentsline{section}{Vector Park Transform}{\pageref{group__park}}{}
\item \contentsline{section}{Vector Inverse Park transform}{\pageref{group__inv__park}}{}
\item \contentsline{section}{Sine Cosine}{\pageref{group___sin_cos}}{}
\end{DoxyCompactList}
\item \contentsline{section}{Statistics Functions}{\pageref{group__group_stats}}{}
\item \contentsline{section}{Support Functions}{\pageref{group__group_support}}{}
\item \contentsline{section}{Interpolation Functions}{\pageref{group__group_interpolation}}{}
\begin{DoxyCompactList}
\item \contentsline{section}{Linear Interpolation}{\pageref{group___linear_interpolate}}{}
\item \contentsline{section}{Bilinear Interpolation}{\pageref{group___bilinear_interpolate}}{}
\end{DoxyCompactList}
\item \contentsline{section}{Examples}{\pageref{group__group_examples}}{}
\item \contentsline{section}{SVM Functions}{\pageref{group__group_s_v_m}}{}
\item \contentsline{section}{Bayesian estimators}{\pageref{group__group_bayes}}{}
\item \contentsline{section}{Distance functions}{\pageref{group__group_distance}}{}
\item \contentsline{section}{Quaternion Math Functions}{\pageref{group__group_quaternion_math}}{}
\item \contentsline{section}{Window Functions}{\pageref{group__group_window}}{}
\item \contentsline{section}{x\+Co\+Routine\+Create}{\pageref{group__x_co_routine_create}}{}
\item \contentsline{section}{v\+Co\+Routine\+Schedule}{\pageref{group__v_co_routine_schedule}}{}
\item \contentsline{section}{cr\+START}{\pageref{group__cr_s_t_a_r_t}}{}
\item \contentsline{section}{cr\+DELAY}{\pageref{group__cr_d_e_l_a_y}}{}
\item \contentsline{section}{cr\+QUEUE\+\_\+\+SEND}{\pageref{group__cr_q_u_e_u_e___s_e_n_d}}{}
\item \contentsline{section}{cr\+QUEUE\+\_\+\+RECEIVE}{\pageref{group__cr_q_u_e_u_e___r_e_c_e_i_v_e}}{}
\item \contentsline{section}{cr\+QUEUE\+\_\+\+SEND\+\_\+\+FROM\+\_\+\+ISR}{\pageref{group__cr_q_u_e_u_e___s_e_n_d___f_r_o_m___i_s_r}}{}
\item \contentsline{section}{cr\+QUEUE\+\_\+\+RECEIVE\+\_\+\+FROM\+\_\+\+ISR}{\pageref{group__cr_q_u_e_u_e___r_e_c_e_i_v_e___f_r_o_m___i_s_r}}{}
\item \contentsline{section}{Event\+Group}{\pageref{group___event_group}}{}
\begin{DoxyCompactList}
\item \contentsline{section}{Event\+Group\+Handle\+\_\+t}{\pageref{group___event_group_handle__t}}{}
\item \contentsline{section}{x\+Event\+Group\+Create}{\pageref{group__x_event_group_create}}{}
\item \contentsline{section}{x\+Event\+Group\+Wait\+Bits}{\pageref{group__x_event_group_wait_bits}}{}
\item \contentsline{section}{x\+Event\+Group\+Clear\+Bits}{\pageref{group__x_event_group_clear_bits}}{}
\item \contentsline{section}{x\+Event\+Group\+Clear\+Bits\+From\+ISR}{\pageref{group__x_event_group_clear_bits_from_i_s_r}}{}
\item \contentsline{section}{x\+Event\+Group\+Set\+Bits}{\pageref{group__x_event_group_set_bits}}{}
\item \contentsline{section}{x\+Event\+Group\+Set\+Bits\+From\+ISR}{\pageref{group__x_event_group_set_bits_from_i_s_r}}{}
\item \contentsline{section}{x\+Event\+Group\+Sync}{\pageref{group__x_event_group_sync}}{}
\item \contentsline{section}{x\+Event\+Group\+Get\+Bits}{\pageref{group__x_event_group_get_bits}}{}
\item \contentsline{section}{x\+Event\+Group\+Get\+Bits\+From\+ISR}{\pageref{group__x_event_group_get_bits_from_i_s_r}}{}
\end{DoxyCompactList}
\item \contentsline{section}{x\+Message\+Buffer\+Create}{\pageref{group__x_message_buffer_create}}{}
\item \contentsline{section}{x\+Message\+Buffer\+Create\+Static}{\pageref{group__x_message_buffer_create_static}}{}
\item \contentsline{section}{x\+Message\+Buffer\+Send}{\pageref{group__x_message_buffer_send}}{}
\item \contentsline{section}{x\+Message\+Buffer\+Send\+From\+ISR}{\pageref{group__x_message_buffer_send_from_i_s_r}}{}
\item \contentsline{section}{x\+Message\+Buffer\+Receive}{\pageref{group__x_message_buffer_receive}}{}
\item \contentsline{section}{x\+Message\+Buffer\+Receive\+From\+ISR}{\pageref{group__x_message_buffer_receive_from_i_s_r}}{}
\item \contentsline{section}{x\+Message\+Buffer\+Reset}{\pageref{group__x_message_buffer_reset}}{}
\item \contentsline{section}{x\+Message\+Buffer\+Space\+Available}{\pageref{group__x_message_buffer_space_available}}{}
\item \contentsline{section}{x\+Message\+Buffer\+Next\+Length\+Bytes}{\pageref{group__x_message_buffer_next_length_bytes}}{}
\item \contentsline{section}{x\+Message\+Buffer\+Send\+Completed\+From\+ISR}{\pageref{group__x_message_buffer_send_completed_from_i_s_r}}{}
\item \contentsline{section}{x\+Message\+Buffer\+Receive\+Completed\+From\+ISR}{\pageref{group__x_message_buffer_receive_completed_from_i_s_r}}{}
\item \contentsline{section}{x\+Queue\+Create}{\pageref{group__x_queue_create}}{}
\item \contentsline{section}{x\+Queue\+Create\+Static}{\pageref{group__x_queue_create_static}}{}
\item \contentsline{section}{x\+Queue\+Send}{\pageref{group__x_queue_send}}{}
\item \contentsline{section}{x\+Queue\+Overwrite}{\pageref{group__x_queue_overwrite}}{}
\item \contentsline{section}{x\+Queue\+Peek}{\pageref{group__x_queue_peek}}{}
\item \contentsline{section}{x\+Queue\+Peek\+From\+ISR}{\pageref{group__x_queue_peek_from_i_s_r}}{}
\item \contentsline{section}{x\+Queue\+Receive}{\pageref{group__x_queue_receive}}{}
\item \contentsline{section}{ux\+Queue\+Messages\+Waiting}{\pageref{group__ux_queue_messages_waiting}}{}
\item \contentsline{section}{v\+Queue\+Delete}{\pageref{group__v_queue_delete}}{}
\item \contentsline{section}{x\+Queue\+Send\+From\+ISR}{\pageref{group__x_queue_send_from_i_s_r}}{}
\item \contentsline{section}{x\+Queue\+Overwrite\+From\+ISR}{\pageref{group__x_queue_overwrite_from_i_s_r}}{}
\item \contentsline{section}{x\+Queue\+Receive\+From\+ISR}{\pageref{group__x_queue_receive_from_i_s_r}}{}
\item \contentsline{section}{v\+Semaphore\+Create\+Binary}{\pageref{group__v_semaphore_create_binary}}{}
\item \contentsline{section}{x\+Semaphore\+Create\+Binary}{\pageref{group__x_semaphore_create_binary}}{}
\item \contentsline{section}{x\+Semaphore\+Create\+Binary\+Static}{\pageref{group__x_semaphore_create_binary_static}}{}
\item \contentsline{section}{x\+Semaphore\+Take}{\pageref{group__x_semaphore_take}}{}
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\item \contentsline{section}{FLASH Type Erase}{\pageref{group___f_l_a_s_h_ex___type___erase}}{}
\item \contentsline{section}{FLASH WRP State}{\pageref{group___f_l_a_s_h_ex___w_r_p___state}}{}
\item \contentsline{section}{FLASH Option Type}{\pageref{group___f_l_a_s_h_ex___option___type}}{}
\item \contentsline{section}{FLASH Option Bytes Read Protection}{\pageref{group___f_l_a_s_h_ex___option___bytes___read___protection}}{}
\item \contentsline{section}{FLASH Option Bytes IWatchdog}{\pageref{group___f_l_a_s_h_ex___option___bytes___i_watchdog}}{}
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\item \contentsline{section}{FLASH IWDG Counter Freeze in STOP}{\pageref{group___f_l_a_s_h_ex___option___bytes___i_w_d_g___f_r_e_e_z_e___s_t_o_p}}{}
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\item \contentsline{section}{FLASH BOR Reset Level}{\pageref{group___f_l_a_s_h_ex___b_o_r___reset___level}}{}
\item \contentsline{section}{FLASH Boot Address}{\pageref{group___f_l_a_s_h_ex___boot___address}}{}
\item \contentsline{section}{FLASH Latency}{\pageref{group___f_l_a_s_h___latency}}{}
\item \contentsline{section}{FLASH Banks}{\pageref{group___f_l_a_s_h_ex___banks}}{}
\item \contentsline{section}{FLASHEx OB PCROP RDP}{\pageref{group___f_l_a_s_h_ex___o_b___p_c_r_o_p___r_d_p}}{}
\item \contentsline{section}{FLASH Option Bytes Write Protection}{\pageref{group___f_l_a_s_h_ex___option___bytes___write___protection}}{}
\item \contentsline{section}{FLASHEx OB SECURITY}{\pageref{group___f_l_a_s_h_ex___o_b___s_e_c_u_r_i_t_y}}{}
\item \contentsline{section}{FLASHEx OB ST RAM SIZE}{\pageref{group___f_l_a_s_h_ex___o_b___s_t___r_a_m___s_i_z_e}}{}
\item \contentsline{section}{FLASHEx OB IWDG1 SW}{\pageref{group___f_l_a_s_h_ex___o_b___i_w_d_g1___s_w}}{}
\item \contentsline{section}{FLASHEx OB NRST STOP D1}{\pageref{group___f_l_a_s_h_ex___o_b___n_r_s_t___s_t_o_p___d1}}{}
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\item \contentsline{section}{FLASHEx OB IOHSLV}{\pageref{group___f_l_a_s_h_ex___o_b___i_o_h_s_l_v}}{}
\item \contentsline{section}{FLASHEx OB USER Type}{\pageref{group___f_l_a_s_h_ex___o_b___u_s_e_r___type}}{}
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\item \contentsline{section}{IRQ Handler and Callbacks}{\pageref{group___i2_c___i_r_q___handler__and___callbacks}}{}
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\item \contentsline{section}{MDMA Transfer Trigger Mode}{\pageref{group___m_d_m_a___transfer___trigger_mode}}{}
\item \contentsline{section}{MDMA Priority level}{\pageref{group___m_d_m_a___priority__level}}{}
\item \contentsline{section}{MDMA Endianness}{\pageref{group___m_d_m_a___endianness}}{}
\item \contentsline{section}{MDMA Source increment mode}{\pageref{group___m_d_m_a___source__increment__mode}}{}
\item \contentsline{section}{MDMA Destination increment mode}{\pageref{group___m_d_m_a___destination__increment__mode}}{}
\item \contentsline{section}{MDMA Source data size}{\pageref{group___m_d_m_a___source__data__size}}{}
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\item \contentsline{section}{PWR Regulator state in SLEEP/\+STOP mode}{\pageref{group___p_w_r___regulator__state__in___s_t_o_p__mode}}{}
\item \contentsline{section}{PWR SLEEP mode entry}{\pageref{group___p_w_r___s_l_e_e_p__mode__entry}}{}
\item \contentsline{section}{PWR STOP mode entry}{\pageref{group___p_w_r___s_t_o_p__mode__entry}}{}
\item \contentsline{section}{PWR Regulator Voltage Scale}{\pageref{group___p_w_r___regulator___voltage___scale}}{}
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\item \contentsline{section}{Peripherals control functions}{\pageref{group___p_w_r_ex___exported___functions___group3}}{}
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\item \contentsline{section}{RCC HSI Config}{\pageref{group___r_c_c___h_s_i___config}}{}
\item \contentsline{section}{RCC HSI48 Config}{\pageref{group___r_c_c___h_s_i48___config}}{}
\item \contentsline{section}{RCC LSI Config}{\pageref{group___r_c_c___l_s_i___config}}{}
\item \contentsline{section}{RCC CSI Config}{\pageref{group___r_c_c___c_s_i___config}}{}
\item \contentsline{section}{RCC PLL Config}{\pageref{group___r_c_c___p_l_l___config}}{}
\item \contentsline{section}{RCC PLL Clock Source}{\pageref{group___r_c_c___p_l_l___clock___source}}{}
\item \contentsline{section}{RCC PLL Clock Output}{\pageref{group___r_c_c___p_l_l___clock___output}}{}
\item \contentsline{section}{RCC PLL1 VCI Range}{\pageref{group___r_c_c___p_l_l1___v_c_i___range}}{}
\item \contentsline{section}{RCC PLL1 VCO Range}{\pageref{group___r_c_c___p_l_l1___v_c_o___range}}{}
\item \contentsline{section}{RCC System Clock Type}{\pageref{group___r_c_c___system___clock___type}}{}
\item \contentsline{section}{RCC System Clock Source}{\pageref{group___r_c_c___system___clock___source}}{}
\item \contentsline{section}{System Clock Source Status}{\pageref{group___r_c_c___system___clock___source___status}}{}
\item \contentsline{section}{RCC SYS Clock Source}{\pageref{group___r_c_c___s_y_s___clock___source}}{}
\item \contentsline{section}{RCC HCLK Clock Source}{\pageref{group___r_c_c___h_c_l_k___clock___source}}{}
\item \contentsline{section}{RCC APB3 Clock Source}{\pageref{group___r_c_c___a_p_b3___clock___source}}{}
\item \contentsline{section}{RCC APB1 Clock Source}{\pageref{group___r_c_c___a_p_b1___clock___source}}{}
\item \contentsline{section}{RCC APB2 Clock Source}{\pageref{group___r_c_c___a_p_b2___clock___source}}{}
\item \contentsline{section}{RCC APB4 Clock Source}{\pageref{group___r_c_c___a_p_b4___clock___source}}{}
\item \contentsline{section}{RCC RTC Clock Source}{\pageref{group___r_c_c___r_t_c___clock___source}}{}
\item \contentsline{section}{RCC MCO Index}{\pageref{group___r_c_c___m_c_o___index}}{}
\item \contentsline{section}{RCC MCO1 Clock Source}{\pageref{group___r_c_c___m_c_o1___clock___source}}{}
\item \contentsline{section}{RCC MCO2 Clock Source}{\pageref{group___r_c_c___m_c_o2___clock___source}}{}
\item \contentsline{section}{RCC MCOx Clock Prescaler}{\pageref{group___r_c_c___m_c_ox___clock___prescaler}}{}
\item \contentsline{section}{RCC Interrupt}{\pageref{group___r_c_c___interrupt}}{}
\item \contentsline{section}{RCC Flag}{\pageref{group___r_c_c___flag}}{}
\item \contentsline{section}{LSE Drive Config}{\pageref{group___r_c_c___l_s_e_drive___config}}{}
\item \contentsline{section}{RCC Stop Wake\+Up\+Clock}{\pageref{group___r_c_c___stop___wake_up_clock}}{}
\item \contentsline{section}{RCC Stop Kernel\+Wake\+Up\+Clock}{\pageref{group___r_c_c___stop___kernel_wake_up_clock}}{}
\end{DoxyCompactList}
\item \contentsline{section}{RCC Exported Macros}{\pageref{group___r_c_c___exported___macros}}{}
\begin{DoxyCompactList}
\item \contentsline{section}{LSE Configuration}{\pageref{group___r_c_c___l_s_e___configuration}}{}
\item \contentsline{section}{RCC Extended MCOx Clock Config}{\pageref{group___r_c_c_ex___m_c_ox___clock___config}}{}
\item \contentsline{section}{Flags Interrupts Management}{\pageref{group___r_c_c___flags___interrupts___management}}{}
\end{DoxyCompactList}
\item \contentsline{section}{RCC Private Constants}{\pageref{group___r_c_c___private___constants}}{}
\item \contentsline{section}{RCC\+\_\+\+Exported\+\_\+\+Functions}{\pageref{group___r_c_c___exported___functions}}{}
\begin{DoxyCompactList}
\item \contentsline{section}{RCC\+\_\+\+Exported\+\_\+\+Functions\+\_\+\+Group1}{\pageref{group___r_c_c___exported___functions___group1}}{}
\item \contentsline{section}{RCC\+\_\+\+Exported\+\_\+\+Functions\+\_\+\+Group2}{\pageref{group___r_c_c___exported___functions___group2}}{}
\end{DoxyCompactList}
\item \contentsline{section}{RCC Private Macros}{\pageref{group___r_c_c___private___macros}}{}
\begin{DoxyCompactList}
\item \contentsline{section}{RCC Private macros to check input parameters}{\pageref{group___r_c_c___i_s___r_c_c___definitions}}{}
\end{DoxyCompactList}
\end{DoxyCompactList}
\item \contentsline{section}{RCCEx}{\pageref{group___r_c_c_ex}}{}
\begin{DoxyCompactList}
\item \contentsline{section}{RCCEx Exported Types}{\pageref{group___r_c_c_ex___exported___types}}{}
\item \contentsline{section}{RCCEx Exported Constants}{\pageref{group___r_c_c_ex___exported___constants}}{}
\begin{DoxyCompactList}
\item \contentsline{section}{RCCEx Periph Clock Selection}{\pageref{group___r_c_c_ex___periph___clock___selection}}{}
\item \contentsline{section}{RCC PLL2 Clock Output}{\pageref{group___r_c_c___p_l_l2___clock___output}}{}
\item \contentsline{section}{RCC PLL3 Clock Output}{\pageref{group___r_c_c___p_l_l3___clock___output}}{}
\item \contentsline{section}{RCC PLL2 VCI Range}{\pageref{group___r_c_c___p_l_l2___v_c_i___range}}{}
\item \contentsline{section}{RCC PLL2 VCO Range}{\pageref{group___r_c_c___p_l_l2___v_c_o___range}}{}
\item \contentsline{section}{RCC PLL3 VCI Range}{\pageref{group___r_c_c___p_l_l3___v_c_i___range}}{}
\item \contentsline{section}{RCC PLL3 VCO Range}{\pageref{group___r_c_c___p_l_l3___v_c_o___range}}{}
\item \contentsline{section}{RCCEx USART1/6 Clock Source}{\pageref{group___r_c_c_ex___u_s_a_r_t16___clock___source}}{}
\item \contentsline{section}{RCCEx USART1 Clock Source}{\pageref{group___r_c_c_ex___u_s_a_r_t1___clock___source}}{}
\item \contentsline{section}{RCCEx USART6 Clock Source}{\pageref{group___r_c_c_ex___u_s_a_r_t6___clock___source}}{}
\item \contentsline{section}{RCCEx USART2/3/4/5/7/8 Clock Source}{\pageref{group___r_c_c_ex___u_s_a_r_t234578___clock___source}}{}
\item \contentsline{section}{RCCEx USART2 Clock Source}{\pageref{group___r_c_c_ex___u_s_a_r_t2___clock___source}}{}
\item \contentsline{section}{RCCEx USART3 Clock Source}{\pageref{group___r_c_c_ex___u_s_a_r_t3___clock___source}}{}
\item \contentsline{section}{RCCEx UART4 Clock Source}{\pageref{group___r_c_c_ex___u_a_r_t4___clock___source}}{}
\item \contentsline{section}{RCCEx UART5 Clock Source}{\pageref{group___r_c_c_ex___u_a_r_t5___clock___source}}{}
\item \contentsline{section}{RCCEx UART7 Clock Source}{\pageref{group___r_c_c_ex___u_a_r_t7___clock___source}}{}
\item \contentsline{section}{RCCEx UART8 Clock Source}{\pageref{group___r_c_c_ex___u_a_r_t8___clock___source}}{}
\item \contentsline{section}{RCCEx LPUART1 Clock Source}{\pageref{group___r_c_c_ex___l_p_u_a_r_t1___clock___source}}{}
\item \contentsline{section}{RCCEx I2\+C1/2/3/5 Clock Source}{\pageref{group___r_c_c_ex___i2_c1235___clock___source}}{}
\item \contentsline{section}{RCCEx I2\+C1 Clock Source}{\pageref{group___r_c_c_ex___i2_c1___clock___source}}{}
\item \contentsline{section}{RCCEx I2\+C2 Clock Source}{\pageref{group___r_c_c_ex___i2_c2___clock___source}}{}
\item \contentsline{section}{RCCEx I2\+C3 Clock Source}{\pageref{group___r_c_c_ex___i2_c3___clock___source}}{}
\item \contentsline{section}{RCCEx I2\+C4 Clock Source}{\pageref{group___r_c_c_ex___i2_c4___clock___source}}{}
\item \contentsline{section}{RCCEx RNG Clock Source}{\pageref{group___r_c_c_ex___r_n_g___clock___source}}{}
\item \contentsline{section}{RCCEx USB Clock Source}{\pageref{group___r_c_c_ex___u_s_b___clock___source}}{}
\item \contentsline{section}{SAI1 Clock Source}{\pageref{group___r_c_c_ex___s_a_i1___clock___source}}{}
\item \contentsline{section}{SPI1/2/3 Clock Source}{\pageref{group___r_c_c_ex___s_p_i123___clock___source}}{}
\item \contentsline{section}{SPI1 Clock Source}{\pageref{group___r_c_c_ex___s_p_i1___clock___source}}{}
\item \contentsline{section}{SPI2 Clock Source}{\pageref{group___r_c_c_ex___s_p_i2___clock___source}}{}
\item \contentsline{section}{SPI3 Clock Source}{\pageref{group___r_c_c_ex___s_p_i3___clock___source}}{}
\item \contentsline{section}{SPI4/5 Clock Source}{\pageref{group___r_c_c_ex___s_p_i45___clock___source}}{}
\item \contentsline{section}{SPI4 Clock Source}{\pageref{group___r_c_c_ex___s_p_i4___clock___source}}{}
\item \contentsline{section}{SPI5 Clock Source}{\pageref{group___r_c_c_ex___s_p_i5___clock___source}}{}
\item \contentsline{section}{SPI6 Clock Source}{\pageref{group___r_c_c_ex___s_p_i6___clock___source}}{}
\item \contentsline{section}{RCCEx LPTIM1 Clock Source}{\pageref{group___r_c_c_ex___l_p_t_i_m1___clock___source}}{}
\item \contentsline{section}{RCCEx LPTIM2 Clock Source}{\pageref{group___r_c_c_ex___l_p_t_i_m2___clock___source}}{}
\item \contentsline{section}{RCCEx LPTIM3/4/5 Clock Source}{\pageref{group___r_c_c_ex___l_p_t_i_m345___clock___source}}{}
\item \contentsline{section}{RCCEx LPTIM3 Clock Source}{\pageref{group___r_c_c_ex___l_p_t_i_m3___clock___source}}{}
\item \contentsline{section}{RCCEx FMC Clock Source}{\pageref{group___r_c_c_ex___f_m_c___clock___source}}{}
\item \contentsline{section}{RCCEx SDMMC Clock Source}{\pageref{group___r_c_c_ex___s_d_m_m_c___clock___source}}{}
\item \contentsline{section}{RCCEx ADC Clock Source}{\pageref{group___r_c_c_ex___a_d_c___clock___source}}{}
\item \contentsline{section}{RCCEx SWPMI1 Clock Source}{\pageref{group___r_c_c_ex___s_w_p_m_i1___clock___source}}{}
\item \contentsline{section}{RCCEx DFSDM1 Clock Source}{\pageref{group___r_c_c_ex___d_f_s_d_m1___clock___source}}{}
\item \contentsline{section}{RCCEx SPDIFRX Clock Source}{\pageref{group___r_c_c_ex___s_p_d_i_f_r_x___clock___source}}{}
\item \contentsline{section}{RCCEx CEC Clock Source}{\pageref{group___r_c_c_ex___c_e_c___clock___source}}{}
\item \contentsline{section}{RCCEx CLKP Clock Source}{\pageref{group___r_c_c_ex___c_l_k_p___clock___source}}{}
\item \contentsline{section}{RCCEx TIM Prescaler Selection}{\pageref{group___r_c_c_ex___t_i_m___prescaler___selection}}{}
\item \contentsline{section}{RCCEx RCC WWDGx}{\pageref{group___r_c_c_ex___r_c_c___w_w_d_gx}}{}
\item \contentsline{section}{RCC LSE CSS external interrupt line}{\pageref{group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s}}{}
\item \contentsline{section}{RCCEx CRS Status}{\pageref{group___r_c_c_ex___c_r_s___status}}{}
\item \contentsline{section}{RCCEx CRS Synchro\+Source}{\pageref{group___r_c_c_ex___c_r_s___synchro_source}}{}
\item \contentsline{section}{RCCEx CRS Synchro\+Divider}{\pageref{group___r_c_c_ex___c_r_s___synchro_divider}}{}
\item \contentsline{section}{RCCEx CRS Synchro\+Polarity}{\pageref{group___r_c_c_ex___c_r_s___synchro_polarity}}{}
\item \contentsline{section}{RCCEx CRS Reload\+Value\+Default}{\pageref{group___r_c_c_ex___c_r_s___reload_value_default}}{}
\item \contentsline{section}{RCCEx CRS Error\+Limit\+Default}{\pageref{group___r_c_c_ex___c_r_s___error_limit_default}}{}
\item \contentsline{section}{RCCEx CRS HSI48\+Calibration\+Default}{\pageref{group___r_c_c_ex___c_r_s___h_s_i48_calibration_default}}{}
\item \contentsline{section}{RCCEx CRS Freq\+Error\+Direction}{\pageref{group___r_c_c_ex___c_r_s___freq_error_direction}}{}
\item \contentsline{section}{RCCEx CRS Interrupt Sources}{\pageref{group___r_c_c_ex___c_r_s___interrupt___sources}}{}
\item \contentsline{section}{RCCEx CRS Flags}{\pageref{group___r_c_c_ex___c_r_s___flags}}{}
\end{DoxyCompactList}
\item \contentsline{section}{RCCEx Exported Macros}{\pageref{group___r_c_c_ex___exported___macros}}{}
\begin{DoxyCompactList}
\item \contentsline{section}{RCCEx CRS Extended Features}{\pageref{group___r_c_c_ex___c_r_s___extended___features}}{}
\end{DoxyCompactList}
\item \contentsline{section}{RCCEx\+\_\+\+Exported\+\_\+\+Functions}{\pageref{group___r_c_c_ex___exported___functions}}{}
\begin{DoxyCompactList}
\item \contentsline{section}{RCCEx\+\_\+\+Exported\+\_\+\+Functions\+\_\+\+Group1}{\pageref{group___r_c_c_ex___exported___functions___group1}}{}
\item \contentsline{section}{RCCEx\+\_\+\+Exported\+\_\+\+Functions\+\_\+\+Group2}{\pageref{group___r_c_c_ex___exported___functions___group2}}{}
\item \contentsline{section}{RCCEx\+\_\+\+Exported\+\_\+\+Functions\+\_\+\+Group3}{\pageref{group___r_c_c_ex___exported___functions___group3}}{}
\end{DoxyCompactList}
\item \contentsline{section}{RCCEx Private Macros}{\pageref{group___r_c_c_ex___private___macros}}{}
\begin{DoxyCompactList}
\item \contentsline{section}{RCC Private macros to check input parameters}{\pageref{group___r_c_c_ex___i_s___r_c_c___definitions}}{}
\end{DoxyCompactList}
\end{DoxyCompactList}
\item \contentsline{section}{SPI}{\pageref{group___s_p_i}}{}
\begin{DoxyCompactList}
\item \contentsline{section}{SPI Exported Types}{\pageref{group___s_p_i___exported___types}}{}
\item \contentsline{section}{SPI Exported Constants}{\pageref{group___s_p_i___exported___constants}}{}
\begin{DoxyCompactList}
\item \contentsline{section}{SPI FIFO Type}{\pageref{group___s_p_i___f_i_f_o___type}}{}
\item \contentsline{section}{SPI Error Codes}{\pageref{group___s_p_i___error___code}}{}
\item \contentsline{section}{SPI Mode}{\pageref{group___s_p_i___mode}}{}
\item \contentsline{section}{SPI Direction Mode}{\pageref{group___s_p_i___direction}}{}
\item \contentsline{section}{SPI Data Size}{\pageref{group___s_p_i___data___size}}{}
\item \contentsline{section}{SPI Clock Polarity}{\pageref{group___s_p_i___clock___polarity}}{}
\item \contentsline{section}{SPI Clock Phase}{\pageref{group___s_p_i___clock___phase}}{}
\item \contentsline{section}{SPI Slave Select Management}{\pageref{group___s_p_i___slave___select___management}}{}
\item \contentsline{section}{SPI NSS Pulse Mode}{\pageref{group___s_p_i___n_s_s_p___mode}}{}
\item \contentsline{section}{SPI Baud\+Rate Prescaler}{\pageref{group___s_p_i___baud_rate___prescaler}}{}
\item \contentsline{section}{SPI MSB LSB Transmission}{\pageref{group___s_p_i___m_s_b___l_s_b___transmission}}{}
\item \contentsline{section}{SPI TI Mode}{\pageref{group___s_p_i___t_i___mode}}{}
\item \contentsline{section}{SPI CRC Calculation}{\pageref{group___s_p_i___c_r_c___calculation}}{}
\item \contentsline{section}{SPI CRC Length}{\pageref{group___s_p_i___c_r_c__length}}{}
\item \contentsline{section}{SPI Fifo Threshold}{\pageref{group___s_p_i___fifo___threshold}}{}
\item \contentsline{section}{SPI CRC Calculation Initialization Pattern}{\pageref{group___s_p_i___c_r_c___calculation___initialization___pattern}}{}
\item \contentsline{section}{SPI NSS Polarity}{\pageref{group___s_p_i___n_s_s___polarity}}{}
\item \contentsline{section}{Keep IO State}{\pageref{group___s_p_i___master___keep___i_o___state}}{}
\item \contentsline{section}{Control SPI IO Swap}{\pageref{group___s_p_i___i_o___swap}}{}
\item \contentsline{section}{SPI Master SS Idleness}{\pageref{group___s_p_i___master___s_s___idleness}}{}
\item \contentsline{section}{SPI Master Inter-\/\+Data Idleness}{\pageref{group___s_p_i___master___inter_data___idleness}}{}
\item \contentsline{section}{SPI Master Receiver Auto\+Suspend}{\pageref{group___s_p_i___master___r_x___auto_suspend}}{}
\item \contentsline{section}{SPI Underrun Behavior}{\pageref{group___s_p_i___underrun___behaviour}}{}
\item \contentsline{section}{SPI Underrun Detection}{\pageref{group___s_p_i___underrun___detection}}{}
\item \contentsline{section}{SPI Interrupt Definition}{\pageref{group___s_p_i___interrupt__definition}}{}
\item \contentsline{section}{SPI Flags Definition}{\pageref{group___s_p_i___flags__definition}}{}
\item \contentsline{section}{SPI Reception FIFO Status Level}{\pageref{group___s_p_i__reception__fifo__status__level}}{}
\end{DoxyCompactList}
\item \contentsline{section}{SPI Exported Macros}{\pageref{group___s_p_i___exported___macros}}{}
\item \contentsline{section}{SPI Private Macros}{\pageref{group___s_p_i___private___macros}}{}
\item \contentsline{section}{SPI\+\_\+\+Exported\+\_\+\+Functions}{\pageref{group___s_p_i___exported___functions}}{}
\begin{DoxyCompactList}
\item \contentsline{section}{Initialization and de-\/initialization functions}{\pageref{group___s_p_i___exported___functions___group1}}{}
\item \contentsline{section}{IO operation functions}{\pageref{group___s_p_i___exported___functions___group2}}{}
\item \contentsline{section}{Peripheral State and Errors functions}{\pageref{group___s_p_i___exported___functions___group3}}{}
\end{DoxyCompactList}
\end{DoxyCompactList}
\item \contentsline{section}{SPIEx}{\pageref{group___s_p_i_ex}}{}
\begin{DoxyCompactList}
\item \contentsline{section}{SPIEx Exported Types}{\pageref{group___s_p_i_ex___exported___types}}{}
\item \contentsline{section}{SPIEx Exported Constants}{\pageref{group___s_p_i_ex___exported___constants}}{}
\item \contentsline{section}{SPIEx Extended Exported Macros}{\pageref{group___s_p_i_ex___exported___macros}}{}
\item \contentsline{section}{SPIEx\+\_\+\+Exported\+\_\+\+Functions}{\pageref{group___s_p_i_ex___exported___functions}}{}
\begin{DoxyCompactList}
\item \contentsline{section}{SPIEx\+\_\+\+Exported\+\_\+\+Functions\+\_\+\+Group1}{\pageref{group___s_p_i_ex___exported___functions___group1}}{}
\end{DoxyCompactList}
\end{DoxyCompactList}
\item \contentsline{section}{TIM}{\pageref{group___t_i_m}}{}
\begin{DoxyCompactList}
\item \contentsline{section}{TIM Exported Types}{\pageref{group___t_i_m___exported___types}}{}
\item \contentsline{section}{TIM Exported Constants}{\pageref{group___t_i_m___exported___constants}}{}
\begin{DoxyCompactList}
\item \contentsline{section}{TIM Clear Input Source}{\pageref{group___t_i_m___clear_input___source}}{}
\item \contentsline{section}{TIM DMA Base Address}{\pageref{group___t_i_m___d_m_a___base__address}}{}
\item \contentsline{section}{TIM Event Source}{\pageref{group___t_i_m___event___source}}{}
\item \contentsline{section}{TIM Input Channel polarity}{\pageref{group___t_i_m___input___channel___polarity}}{}
\item \contentsline{section}{TIM ETR Polarity}{\pageref{group___t_i_m___e_t_r___polarity}}{}
\item \contentsline{section}{TIM ETR Prescaler}{\pageref{group___t_i_m___e_t_r___prescaler}}{}
\item \contentsline{section}{TIM Counter Mode}{\pageref{group___t_i_m___counter___mode}}{}
\item \contentsline{section}{TIM Update Interrupt Flag Remap}{\pageref{group___t_i_m___update___interrupt___flag___remap}}{}
\item \contentsline{section}{TIM Clock Division}{\pageref{group___t_i_m___clock_division}}{}
\item \contentsline{section}{TIM Output Compare State}{\pageref{group___t_i_m___output___compare___state}}{}
\item \contentsline{section}{TIM Auto-\/\+Reload Preload}{\pageref{group___t_i_m___auto_reload_preload}}{}
\item \contentsline{section}{TIM Output Fast State}{\pageref{group___t_i_m___output___fast___state}}{}
\item \contentsline{section}{TIM Complementary Output Compare State}{\pageref{group___t_i_m___output___compare___n___state}}{}
\item \contentsline{section}{TIM Output Compare Polarity}{\pageref{group___t_i_m___output___compare___polarity}}{}
\item \contentsline{section}{TIM Complementary Output Compare Polarity}{\pageref{group___t_i_m___output___compare___n___polarity}}{}
\item \contentsline{section}{TIM Output Compare Idle State}{\pageref{group___t_i_m___output___compare___idle___state}}{}
\item \contentsline{section}{TIM Complementary Output Compare Idle State}{\pageref{group___t_i_m___output___compare___n___idle___state}}{}
\item \contentsline{section}{TIM Input Capture Polarity}{\pageref{group___t_i_m___input___capture___polarity}}{}
\item \contentsline{section}{TIM Encoder Input Polarity}{\pageref{group___t_i_m___encoder___input___polarity}}{}
\item \contentsline{section}{TIM Input Capture Selection}{\pageref{group___t_i_m___input___capture___selection}}{}
\item \contentsline{section}{TIM Input Capture Prescaler}{\pageref{group___t_i_m___input___capture___prescaler}}{}
\item \contentsline{section}{TIM One Pulse Mode}{\pageref{group___t_i_m___one___pulse___mode}}{}
\item \contentsline{section}{TIM Encoder Mode}{\pageref{group___t_i_m___encoder___mode}}{}
\item \contentsline{section}{TIM interrupt Definition}{\pageref{group___t_i_m___interrupt__definition}}{}
\item \contentsline{section}{TIM Commutation Source}{\pageref{group___t_i_m___commutation___source}}{}
\item \contentsline{section}{TIM DMA Sources}{\pageref{group___t_i_m___d_m_a__sources}}{}
\item \contentsline{section}{CCx DMA request selection}{\pageref{group___t_i_m___c_c___d_m_a___request}}{}
\item \contentsline{section}{TIM Flag Definition}{\pageref{group___t_i_m___flag__definition}}{}
\item \contentsline{section}{TIM Channel}{\pageref{group___t_i_m___channel}}{}
\item \contentsline{section}{TIM Clock Source}{\pageref{group___t_i_m___clock___source}}{}
\item \contentsline{section}{TIM Clock Polarity}{\pageref{group___t_i_m___clock___polarity}}{}
\item \contentsline{section}{TIM Clock Prescaler}{\pageref{group___t_i_m___clock___prescaler}}{}
\item \contentsline{section}{TIM Clear Input Polarity}{\pageref{group___t_i_m___clear_input___polarity}}{}
\item \contentsline{section}{TIM Clear Input Prescaler}{\pageref{group___t_i_m___clear_input___prescaler}}{}
\item \contentsline{section}{TIM OSSR Off\+State Selection for Run mode state}{\pageref{group___t_i_m___o_s_s_r___off___state___selection__for___run__mode__state}}{}
\item \contentsline{section}{TIM OSSI Off\+State Selection for Idle mode state}{\pageref{group___t_i_m___o_s_s_i___off___state___selection__for___idle__mode__state}}{}
\item \contentsline{section}{TIM Lock level}{\pageref{group___t_i_m___lock__level}}{}
\item \contentsline{section}{TIM Break Input Enable}{\pageref{group___t_i_m___break___input__enable__disable}}{}
\item \contentsline{section}{TIM Break Input Polarity}{\pageref{group___t_i_m___break___polarity}}{}
\item \contentsline{section}{TIM Break input 2 Enable}{\pageref{group___t_i_m___break2___input__enable__disable}}{}
\item \contentsline{section}{TIM Break Input 2 Polarity}{\pageref{group___t_i_m___break2___polarity}}{}
\item \contentsline{section}{TIM Automatic Output Enable}{\pageref{group___t_i_m___a_o_e___bit___set___reset}}{}
\item \contentsline{section}{TIM Group Channel 5 and Channel 1, 2 or 3}{\pageref{group___t_i_m___group___channel5}}{}
\item \contentsline{section}{TIM Master Mode Selection}{\pageref{group___t_i_m___master___mode___selection}}{}
\item \contentsline{section}{TIM Master Mode Selection 2 (TRGO2)}{\pageref{group___t_i_m___master___mode___selection__2}}{}
\item \contentsline{section}{TIM Master/\+Slave Mode}{\pageref{group___t_i_m___master___slave___mode}}{}
\item \contentsline{section}{TIM Slave mode}{\pageref{group___t_i_m___slave___mode}}{}
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\item \contentsline{section}{TIM TI1 Input Selection}{\pageref{group___t_i_m___t_i1___selection}}{}
\item \contentsline{section}{TIM DMA Burst Length}{\pageref{group___t_i_m___d_m_a___burst___length}}{}
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\item \contentsline{section}{TIM Capture/\+Compare Channel State}{\pageref{group___channel___c_c___state}}{}
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\item \contentsline{section}{TIM Peripheral State functions}{\pageref{group___t_i_m___exported___functions___group10}}{}
\item \contentsline{section}{TIM Time Base functions}{\pageref{group___t_i_m___exported___functions___group1}}{}
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\item \contentsline{section}{TIM One Pulse functions}{\pageref{group___t_i_m___exported___functions___group5}}{}
\item \contentsline{section}{TIM Encoder functions}{\pageref{group___t_i_m___exported___functions___group6}}{}
\item \contentsline{section}{TIM IRQ handler management}{\pageref{group___t_i_m___exported___functions___group7}}{}
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\item \contentsline{section}{Extended Timer Hall Sensor functions}{\pageref{group___t_i_m_ex___exported___functions___group1}}{}
\item \contentsline{section}{Extended Timer Complementary Output Compare functions}{\pageref{group___t_i_m_ex___exported___functions___group2}}{}
\item \contentsline{section}{Extended Timer Complementary PWM functions}{\pageref{group___t_i_m_ex___exported___functions___group3}}{}
\item \contentsline{section}{Extended Timer Complementary One Pulse functions}{\pageref{group___t_i_m_ex___exported___functions___group4}}{}
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\item \contentsline{section}{Extended Callbacks functions}{\pageref{group___t_i_m_ex___exported___functions___group6}}{}
\item \contentsline{section}{Extended Peripheral State functions}{\pageref{group___t_i_m_ex___exported___functions___group7}}{}
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\item \contentsline{section}{UART Exported Types}{\pageref{group___u_a_r_t___exported___types}}{}
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\item \contentsline{section}{UART State Code Definition}{\pageref{group___u_a_r_t___state___definition}}{}
\item \contentsline{section}{UART Error Definition}{\pageref{group___u_a_r_t___error___definition}}{}
\item \contentsline{section}{UART Number of Stop Bits}{\pageref{group___u_a_r_t___stop___bits}}{}
\item \contentsline{section}{UART Parity}{\pageref{group___u_a_r_t___parity}}{}
\item \contentsline{section}{UART Hardware Flow Control}{\pageref{group___u_a_r_t___hardware___flow___control}}{}
\item \contentsline{section}{UART Transfer Mode}{\pageref{group___u_a_r_t___mode}}{}
\item \contentsline{section}{UART State}{\pageref{group___u_a_r_t___state}}{}
\item \contentsline{section}{UART Over Sampling}{\pageref{group___u_a_r_t___over___sampling}}{}
\item \contentsline{section}{UART One Bit Sampling Method}{\pageref{group___u_a_r_t___one_bit___sampling}}{}
\item \contentsline{section}{UART Clock Prescaler}{\pageref{group___u_a_r_t___clock_prescaler}}{}
\item \contentsline{section}{UART Advanced Feature Auto\+Baud Rate Mode}{\pageref{group___u_a_r_t___auto_baud___rate___mode}}{}
\item \contentsline{section}{UART Receiver Timeout}{\pageref{group___u_a_r_t___receiver___timeout}}{}
\item \contentsline{section}{UART Local Interconnection Network mode}{\pageref{group___u_a_r_t___l_i_n}}{}
\item \contentsline{section}{UART LIN Break Detection}{\pageref{group___u_a_r_t___l_i_n___break___detection}}{}
\item \contentsline{section}{UART DMA Tx}{\pageref{group___u_a_r_t___d_m_a___tx}}{}
\item \contentsline{section}{UART DMA Rx}{\pageref{group___u_a_r_t___d_m_a___rx}}{}
\item \contentsline{section}{UART Half Duplex Selection}{\pageref{group___u_a_r_t___half___duplex___selection}}{}
\item \contentsline{section}{UART Wake\+Up Methods}{\pageref{group___u_a_r_t___wake_up___methods}}{}
\item \contentsline{section}{UART Request Parameters}{\pageref{group___u_a_r_t___request___parameters}}{}
\item \contentsline{section}{UART Advanced Feature Initialization Type}{\pageref{group___u_a_r_t___advanced___features___initialization___type}}{}
\item \contentsline{section}{UART Advanced Feature TX Pin Active Level Inversion}{\pageref{group___u_a_r_t___tx___inv}}{}
\item \contentsline{section}{UART Advanced Feature RX Pin Active Level Inversion}{\pageref{group___u_a_r_t___rx___inv}}{}
\item \contentsline{section}{UART Advanced Feature Binary Data Inversion}{\pageref{group___u_a_r_t___data___inv}}{}
\item \contentsline{section}{UART Advanced Feature RX TX Pins Swap}{\pageref{group___u_a_r_t___rx___tx___swap}}{}
\item \contentsline{section}{UART Advanced Feature Overrun Disable}{\pageref{group___u_a_r_t___overrun___disable}}{}
\item \contentsline{section}{UART Advanced Feature Auto Baud\+Rate Enable}{\pageref{group___u_a_r_t___auto_baud_rate___enable}}{}
\item \contentsline{section}{UART Advanced Feature DMA Disable On Rx Error}{\pageref{group___u_a_r_t___d_m_a___disable__on___rx___error}}{}
\item \contentsline{section}{UART Advanced Feature MSB First}{\pageref{group___u_a_r_t___m_s_b___first}}{}
\item \contentsline{section}{UART Advanced Feature Stop Mode Enable}{\pageref{group___u_a_r_t___stop___mode___enable}}{}
\item \contentsline{section}{UART Advanced Feature Mute Mode Enable}{\pageref{group___u_a_r_t___mute___mode}}{}
\item \contentsline{section}{UART Address-\/matching LSB Position In CR2 Register}{\pageref{group___u_a_r_t___c_r2___a_d_d_r_e_s_s___l_s_b___p_o_s}}{}
\item \contentsline{section}{UART Wake\+Up From Stop Selection}{\pageref{group___u_a_r_t___wake_up__from___stop___selection}}{}
\item \contentsline{section}{UART Driver\+Enable Polarity}{\pageref{group___u_a_r_t___driver_enable___polarity}}{}
\item \contentsline{section}{UART Driver Enable Assertion Time LSB Position In CR1 Register}{\pageref{group___u_a_r_t___c_r1___d_e_a_t___a_d_d_r_e_s_s___l_s_b___p_o_s}}{}
\item \contentsline{section}{UART Driver Enable De\+Assertion Time LSB Position In CR1 Register}{\pageref{group___u_a_r_t___c_r1___d_e_d_t___a_d_d_r_e_s_s___l_s_b___p_o_s}}{}
\item \contentsline{section}{UART Interruptions Flag Mask}{\pageref{group___u_a_r_t___interruption___mask}}{}
\item \contentsline{section}{UART polling-\/based communications time-\/out value}{\pageref{group___u_a_r_t___time_out___value}}{}
\item \contentsline{section}{UART Status Flags}{\pageref{group___u_a_r_t___flags}}{}
\item \contentsline{section}{UART Interrupts Definition}{\pageref{group___u_a_r_t___interrupt__definition}}{}
\item \contentsline{section}{UART Interruption Clear Flags}{\pageref{group___u_a_r_t___i_t___c_l_e_a_r___flags}}{}
\item \contentsline{section}{UART Reception type values}{\pageref{group___u_a_r_t___reception___type___values}}{}
\item \contentsline{section}{UART Rx\+Event type values}{\pageref{group___u_a_r_t___rx_event___type___values}}{}
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\item \contentsline{section}{UART Private variables}{\pageref{group___u_a_r_t___private__variables}}{}
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\item \contentsline{section}{Initialization and de-\/initialization functions}{\pageref{group___u_a_r_t___exported___functions___group1}}{}
\item \contentsline{section}{IO operation functions}{\pageref{group___u_a_r_t___exported___functions___group2}}{}
\item \contentsline{section}{Peripheral Control functions}{\pageref{group___u_a_r_t___exported___functions___group3}}{}
\item \contentsline{section}{Peripheral State and Error functions}{\pageref{group___u_a_r_t___exported___functions___group4}}{}
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\item \contentsline{section}{UARTEx}{\pageref{group___u_a_r_t_ex}}{}
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\item \contentsline{section}{UARTEx Exported Types}{\pageref{group___u_a_r_t_ex___exported___types}}{}
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\item \contentsline{section}{UARTEx Word Length}{\pageref{group___u_a_r_t_ex___word___length}}{}
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\item \contentsline{section}{UARTEx FIFO mode}{\pageref{group___u_a_r_t_ex___f_i_f_o__mode}}{}
\item \contentsline{section}{UARTEx TXFIFO threshold level}{\pageref{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level}}{}
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\item \contentsline{section}{GPIOEx}{\pageref{group___g_p_i_o_ex}}{}
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\item \contentsline{section}{GPIO Alternate Function Selection}{\pageref{group___g_p_i_o___alternate__function__selection}}{}
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\item \contentsline{section}{STM32\+H7xx\+\_\+\+LL\+\_\+\+Driver}{\pageref{group___s_t_m32_h7xx___l_l___driver}}{}
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\item \contentsline{section}{CORTEX}{\pageref{group___c_o_r_t_e_x___l_l}}{}
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\item \contentsline{section}{SYSTICK Clock Source}{\pageref{group___c_o_r_t_e_x___l_l___e_c___c_l_k_s_o_u_r_c_e___h_c_l_k}}{}
\item \contentsline{section}{Handler Fault type}{\pageref{group___c_o_r_t_e_x___l_l___e_c___f_a_u_l_t}}{}
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\item \contentsline{section}{LOW POWER MODE}{\pageref{group___c_o_r_t_e_x___l_l___e_f___l_o_w___p_o_w_e_r___m_o_d_e}}{}
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\item \contentsline{section}{UTILS}{\pageref{group___u_t_i_l_s___l_l}}{}
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\item \contentsline{section}{HSE Bypass activation}{\pageref{group___u_t_i_l_s___e_c___h_s_e___b_y_p_a_s_s}}{}
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\item \contentsline{section}{DEVICE ELECTRONIC SIGNATURE}{\pageref{group___u_t_i_l_s___e_f___d_e_v_i_c_e___e_l_e_c_t_r_o_n_i_c___s_i_g_n_a_t_u_r_e}}{}
\item \contentsline{section}{DELAY}{\pageref{group___u_t_i_l_s___l_l___e_f___d_e_l_a_y}}{}
\item \contentsline{section}{SYSTEM}{\pageref{group___u_t_i_l_s___e_f___s_y_s_t_e_m}}{}
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